Digital Circuits
Number systems, combinational and sequential logic, flip-flop timing, counters, memory, and the CMOS behind the gate symbols.
About this subject
Digital Circuits covers how information is represented in binary and how logic gates, flip-flops and memories are combined to process it. It starts with number systems and Boolean algebra, moves through combinational circuits such as multiplexers, decoders and adders, and ends with sequential circuits - flip-flops, counters and state machines - plus the CMOS transistors, converters and memories underneath.
Questions reward clean, systematic working more than cleverness. Most can be solved by writing a truth table, a state table or a timing sum and reading the answer off it, which also makes this one of the best subjects to secure marks in.
Solved questions
Each question is a practice problem written for this portal at GATE standard. Try it first, then open the full derivation, and read the note on the idea behind it.
- MCQ State of a 4-bit synchronous up-counter after 13 clock pulses Counters · 1 mark
- NAT Maximum clock frequency from propagation, logic and setup time Sequential timing · 2 marks
- MCQ Realising a 3-variable function on a 4:1 multiplexer Combinational logic · 2 marks
- NAT Transistor count for a static CMOS AND-OR-INVERT gate CMOS logic · 1 mark
Key formulas
The results these questions lean on most. Know what each symbol means, and when each one applies.
| What | Formula |
|---|---|
| States of an $n$-bit counter | $2^n$; a mod-$N$ counter needs $\lceil \log_2 N \rceil$ flip-flops |
| Minimum clock period | $T_{min} = t_{cq} + t_{logic} + t_{su}$ (plus skew if the capture clock is early) |
| Maximum frequency | $f_{max} = 1 / T_{min}$ |
| Hold condition | $t_{cq,min} + t_{logic,min} \ge t_h$ - the period never appears |
| A $2^n$:1 multiplexer | realises any function of $n+1$ variables, with the last variable on the data inputs |
| Static CMOS complex gate | 2 transistors per input: $n$ in the pull-down, $n$ in the pull-up |
| De Morgan | $\overline{A B} = \overline{A} + \overline{B}$, $\;\overline{A + B} = \overline{A}\,\overline{B}$ |
| $n$-bit DAC resolution | $V_{FS} / (2^n - 1)$ per step (or $V_{ref}/2^n$, depending on the convention) |
How to prepare
- Draw a truth table or a state table before reaching for a formula. It is rarely slower, and it catches mistakes.
- For every sequential question, decide first whether it is about setup (uses the period) or hold (does not).
- Practise converting between SOP, POS, K-maps and multiplexer realisations until it is mechanical.
- Count transistors from the structure of the gate, not from memory: pull-down network, then its dual.
Common traps
Each of these costs marks every year. The questions above are built to catch them.
- Putting hold time into the maximum-frequency sum.
- Swapping the MSB and LSB of a multiplexer's select lines.
- Treating a ripple counter as if all bits change at the same instant.
- Building an AND-OR-INVERT function from separate gates, when one complex gate is smaller and faster.
Learn it in depth
The Hardware Academy teaches this part of the syllabus from zero, with worked examples: